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Mila
Deep Neural Network Library
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The Qwen 3.8-27B per-role weight allocation, as a named plan struct. More...
#include <concepts>import Dnn.Quantization.Weight.PrecisionPlan;import Dnn.Quantization.Weight.Policies;Classes | |
| struct | Mila::Dnn::QwenOraclePrecisionPlan |
| The Section 5 oracle: FP4 across the body, everything else as the plan has it. More... | |
| struct | Mila::Dnn::QwenPrecisionPlan |
| The section 5 allocation: 25.62 B resident weights at 2.90 bits average, 8.65 GiB. More... | |
| struct | Mila::Dnn::QwenPlanDetail::QwenPrecisionPlanSelector< T, kIsBarePolicy > |
| struct | Mila::Dnn::QwenPlanDetail::QwenPrecisionPlanSelector< T, true > |
| struct | Mila::Dnn::QwenUniformPrecisionPlan< TPolicy > |
| One policy across every Qwen role, DeltaNet included. More... | |
Namespaces | |
| namespace | Mila |
| Mila main API namespace. | |
Concepts | |
| concept | Mila::Dnn::DeltaNetPrecisionRoles |
| Roles a Gated DeltaNet block instantiates, on top of the feed-forward pair. | |
Typedefs | |
| template<typename T> | |
| using | Mila::Dnn::QwenPrecisionPlanFor |
| The Qwen lift: accepts a plan or a bare policy, and yields a plan WITH the DeltaNet roles. | |
| using | Mila::Dnn::QwenReferencePrecisionPlan = QwenUniformPrecisionPlan<NoWeightQuant> |
| The reference-precision plan: everything BF16, nothing quantized. | |
The Qwen 3.8-27B per-role weight allocation, as a named plan struct.
This file IS Specifications/Qwen3.8.md section 5, expressed as types. It is the one declaration a reader consults to learn what the model spends its 12 GiB on, which is the property the whole per-role mechanism exists to preserve (section 6).
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The Qwen lift: accepts a plan or a bare policy, and yields a plan WITH the DeltaNet roles.
The generic PrecisionPlanFor cannot serve the DeltaNet block, because the generic uniform plan deliberately does not name this family's roles – a block kind must not be able to invalidate plans that already work. So the family that adds roles adds the lift that carries them, and QwenDeltaNetBlock<Cuda, BF16, PerGroupFp4<128>> stays a valid spelling alongside <..., QwenPrecisionPlan>.
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The reference-precision plan: everything BF16, nothing quantized.
Phase 4 gates the chassis against the HF reference at BF16 before Phase 5 applies the allocation above, so both must be spellable at a declaration site. Named here so the two arms of that comparison read as siblings rather than as a plan and a bare policy.